Dynamic voltage (IR) drop, in contrast to the static voltage drop depends on the switching activity of the design, and hence it is vector dependent.
Designing an ideal power grid which is robust across multiple operating scenarios of a chip continues to major challenge. The problem has magnified with technology shrinking allowing more performance to pack in a smaller area, from one node to another.
The power distribution on a chip needs to make sure circuit robustness catering to not only to the average power / current requirements, but also needs to make sure timing or accuracy not affected by Dynamic IR drop, caused by limited power demand and switching patterns. Further, today’s devices power management techniques like power gating and switch power supplies are measures. In the case of switched power supplies, typically, power switch cells are uniformly distributed across the standard cell logic (logic gates) area of the floor plan.
There may further be sub-divisions in the switched power grid in the form of power domains, depending on the granularity of power gating. These power switches add further dimension to the power distribution problem as they often limit the response of the power grid to dynamic power or electrical needs. While the power distribution can improve easily by increasing the number of power switches, it has an impact on the off mode leakage (Iddq) and hence battery life in handheld applications.
So clearly, it is important to decrease the number of switches used as well as decrease the signal routing resources used on the power grid. Design closure and signoff (timing, IR Drop, EM, reliability etc.) comprehending Dynamic IR drop effects realistically. The factors provide cynicism in Dynamic voltage drop analysis should remove and must make sure the method power coverage of various silicon conditions and design operating scenarios. We then discuss power distribution and power grid planning method, and highlight the various aspects that need to take care of, from the early stages of design implementation. We give some of the systematic power grid enhancements like power automated switch placement and switched supply resistance minimization through DRC-aware power metal fill. All the analysis and results are based on production application of low power application processors for mobile devices.
Static and Dynamic IR Drop
Static IR drop is average voltage drop for the design. While Dynamic IR drop depends on switching activity of the logic, therefore it is vector dependent. Dynamic IR drop depends on the switching time of logic and is less dependent on clock period. This nature illustrated in The Average current depends totally on the time period, while the dynamic IR drop depends on the instantaneous current which is higher while the cell is switching.
Static IR drop is good for closure analysis, in older technology nodes where enough natural decoupling capability from the power network and non-switching logic is available. While Dynamic IR drop measures IR drop caused when large amount of circuitry switch together, causing peak electricity demands. This electrical demand could highly localize and could brief within a single clock cycle (a few hundred PS) and could result in an IR drop that causes further setup or hold-time violations. Usually, high IR drop impact on clock networks causes hold time violations, while IR drop on data path signal nets results setup time violations.
Dynamic Analysis on Power Grid
A normal power grid and power switches designed for regular power. Usually, they designed for appropriate static IR drop objective and not for Dynamic IR drop. In the basic stage of the design, the grid power checks only with the Static IR drop result. This is because of late availability of use case scenarios (Voltage change dump (VCD) files). For the example, the switch and metal grid densities in the notches region can satisfy the static IR drop criteria, because the average power density in this region is not significant.
When an application runs, gap area have higher power density due to limited switching in gap area and the switches combined with metal is not enough to support the electrical density in the gap area. Because of which have very high dynamic IR drop. Here due to less number of switch cells combined with not so powerful grid is the main reason for high dynamic IR drop. As described by the figure, Switch Voltage drop and MET3 voltage drop are the dominant factors in the overall voltage drop. A similar analogy on the power density can extend to larger region.
Dynamic IR Analysis
Difficulties in analysing the dynamic IR impact on SOCs or complex designs is to get direction for enough scenarios and to get them in time to identify issues before the design tapes out. Our Early Analysis flow addresses this issue. In this flow, the switching activity of a sub IP integrated at the top level and switching activity at the top level created, for use in dynamic IR analysis. With the help of flow analysis, we are able to analyse architectural hot spots for dynamic IR drop, like crossbar collaborating shared memories having great power density.